1. Field of the Invention
The present invention relates to a 1Tr-1C (one-transistor and one-capacitor) multiport memory-circuit used as a two-port memory in which write and read clock signals are asynchronous, and particularly to a multiport memory circuit applicable to various purposes as a data buffer between devices with different operation speed such as a FIFO (First-In, First-Out) memory.
2. Description of Related Art
FIFO memories are used for various purposes as a data buffer between devices with different operation speed. The FIFO memory needs two ports because its write and read clock signals are asynchronous (see, prior art reference 1, for example). Accordingly, the conventional FIFO memories are composed of a 3Tr-1C-DRAM or 8Tr-SRAM.
Thus, the write and read clock signals are asynchronous in the conventional FIFO memory. Accordingly, writing to a specified memory cell is carried out using a write bit decoder and a write word decoder. Likewise, reading from a specified memory cell is carried out using a read bit decoder and a read word decoder. Thus, the conventional FIFO memory includes the two word decoders and two bit decoders for writing and reading, which prevents the size reduction in the memory circuit.
Since data in the conventional 3Tr-1C-DRAM memory cells is read nondestructively, the data can be read any number of times as long as the data is held. In addition, the 3Tr-1C-DRAM memory cell can be smaller in size than an 8Tr-1C-SRAM memory cell which will be described later, because it has a smaller number of transistors and capacitors per memory cell. However, since it includes a write selecting circuit at each address, when the number of bits (the number of the memory cells) per address is small, a relative area occupied by the write selecting circuit increases, thereby preventing the miniaturization of the memory cell. Furthermore, a refresh circuit, which is provided for solving the problem of data holding time of the DRAM, will prevent the miniaturization of the memory cell because of its occupying area.
The data in the conventional 8Tr-SRAM memory cells can also be read nondestructively, allowing the data to be read any number of times from the memory cells. In addition, the 8Tr-SRAM memory cells are free from the problem of the data holding because of the SRAM structure. However, they include a greater number of transistors per memory cell than the 3Tr-1C-DRAM memory cells, which prevents the miniaturization of the memory cell.
The following seven relevant references are cited and incorporated herein by reference.
[Reference 1]
Japanese patent application laid-open No. 2001-43674 (paragraph 19 and FIG. 2)
[Reference 2]
Japanese patent application laid-open No. 5-198168/1993 (paragraphs 18-21, and FIG. 1)
[Reference 3]
Japanese patent application laid-open No. 62-287498/1987 (bottom-right column on page 2 to bottom-right column on page 3, and FIG. 1)
[Reference 4]
Japanese patent application laid-open No. 5-206398/1993 (paragraphs 22-51, and FIGS. 1-3)
[Reference 5]
Japanese patent application laid-open No. 58-130494/1983 (top-right column on page 2 to top-left column on page 3, and FIG. 2)
[Reference 6]
Japanese patent application laid-open No. 10-283769/1998 (paragraphs 37-56, and FIGS. 1-4)
[Reference 7]
Japanese patent application laid-open No. 7-296585/1995 (paragraphs 10-19, and FIGS. 1-4)
With the foregoing configuration, the conventional FIFO memory must include two word decoders and two bit decoders for writing and reading because the clock signals for writing and reading are asynchronous. Thus, it has a problem of hampering the miniaturization of the memory cell.
In addition, the 3Tr-71C-DRAM memory cell has the following problems. First, since it requires one write selecting circuit (NOR gate) for each address, when the number of bits (the number of memory cells) per address is small, the relative area occupied by the write selecting circuits increases, which hinders the miniaturization of the memory cell. In addition, the refresh circuit, which is installed to solve the problem of the data holding time, also prevents the miniaturization of the memory cell because of the area it occupies.
Furthermore, since the 8Tr-SRAM memory cell includes a greater number of transistors per memory cell, it has a problem of hindering the miniaturization of the memory cell.
The present invention is implemented to solve the foregoing problems. It is therefore an object of the present invention to provide a multiport memory circuit composed of 1Tr-1C memory cells capable of reducing the area of the memory cell, thereby being able to reduce the chip size.
According to the present invention, there is provided a multiport memory circuit carrying out its write operation and read operation with reference to an internal clock signal with a frequency equal to or greater than double a higher frequency of a write clock signal and read clock signal. Thus, only the bit decoder circuit and word decoder circuit are enough as the decoder circuits needed for the write and read operation, thereby offering an advantage of being able to reduce the chip size.